Power Distribution Network (PDN) Basics in PCB Design
The power distribution network (PDN) is the system that delivers clean, stable voltage to all the ICs on a board. In modern high-speed designs, as clock frequencies rise and supply voltages drop, PDN design has stopped being "a detail to deal with later" and become one of the main topics that determine performance. An inadequate PDN shows up as instability, logic errors, increased EMI and failing EMC tests. In this article we cover the fundamentals of a solid PDN.
Why does the PDN matter?
When an integrated circuit switches, it draws a sudden current from the supply line. Because the line's impedance isn't zero, this sudden demand creates a voltage droop. If the PDN impedance isn't low enough at the relevant frequencies, these droops push the supply voltage out of tolerance and lead to logic errors and jitter. So the essence of PDN design has a single goal: keeping the impedance low across a wide frequency band.
The target impedance concept
A good PDN design starts with "target impedance": a value found by dividing the maximum allowed voltage ripple by the expected transient current. The goal of the design is to keep the PDN impedance below this target at all frequencies of interest. This view lets you choose decoupling capacitors not randomly but to close the impedance gaps in specific frequency ranges.
Decoupling capacitor strategy
A single capacitor value can't cover all frequencies; because every capacitor has a self-resonant frequency (SRF) arising from its own parasitic inductance, and above this frequency it starts to behave inductively. That's why different values are used together in practice:
- Large value (e.g. electrolytic/tantalum, µF range): meets low-frequency, slow current demands and bulk energy storage.
- Medium value (e.g. 100 nF MLCC): general-purpose decoupling; one on each IC's power pin.
- Small value (e.g. 1–10 nF): suppresses high-frequency transitions.
The goal is for capacitors with different SRFs to overlap their impedance curves and create low impedance across a wide band.
Placement and the importance of inductance
The most critical enemy in a PDN is parasitic inductance. Even the best capacitor is useless if connected far from the power pin or with long/thin traces; because the connection inductance destroys the benefit at high frequency. Therefore:
- Place decoupling capacitors as close as possible to the IC's power pins.
- Lower the connection inductance by using short paths and multiple vias in the transition from the capacitor to the plane.
- Put small-value, high-frequency capacitors in the position closest to the pin.
Power and ground planes
Adjacent (closely spaced) power and ground planes create a natural high-frequency capacitance, helping the PDN for free and suppressing inter-plane noise. Avoid unnecessary splits and slots in the planes; the current finding an uninterrupted return path in the reference plane is critical for both the PDN and signal integrity. In stackup design, placing the power/ground planes on close layers makes a noticeable difference.
Example: target impedance calculation
Suppose a core supply is 1.0 V, the allowed ripple is 5% (50 mV) and the expected transient current is 5 A. The target impedance is found by dividing the voltage tolerance by the current:
Ztarget = 50 mV / 5 A = 10 mΩ
This result means the PDN impedance must be kept below 10 mΩ at all relevant frequencies. As frequency rises, you can only achieve this with plane capacitance and correctly placed decoupling capacitors; a single large capacitor is never enough.
Decoupling layers summary
| Layer | Typical value | Role | Placement |
|---|---|---|---|
| Bulk | 10–100 µF | Low frequency, energy store | Near the regulator |
| Medium | 100 nF | General decoupling | Each power pin |
| High frequency | 1–10 nF | Fast transitions | Closest to the pin |
Common mistakes
- Placing the capacitor far from the pin: connection inductance destroys all the benefit at high frequency; closeness to the pin is essential.
- Connecting with a single via: a single via raises the inductance; use multiple vias per pad where possible.
- Splitting the reference plane: a split power/ground plane lengthens the return current and disrupts both the PDN and signal integrity.
- Using a single value: a single type of capacitor can't cover all frequencies; a mix of values for different SRFs is needed.
- Leaving the stackup for last: placing power/ground planes on late and far layers lowers the natural plane capacitance.
Verification
In critical designs, the PDN impedance is verified against the target impedance with simulation at the design stage and by measurement with tools like a VNA after production. Early simulation heads off expensive problems that would otherwise be discovered after the board is made.
Frequently asked questions
How many decoupling capacitors are needed?
The general rule is one 100 nF per power pin; plus one or a few bulk capacitors per IC. The exact number is determined by the current profile and the target impedance.
Can they all be the same value?
They can, but it's not ideal. Different values' different self-resonant frequencies provide low impedance across a wide band; a single value is effective only in a narrow band.
Does plane capacitance replace decoupling capacitors?
No, it complements them. Adjacent power/ground planes help at very high frequency, but discrete decoupling capacitors are still needed for mid frequencies.
Conclusion
A good PDN comes from the combination of a target-impedance focus, a multi-value decoupling strategy, placement that minimizes inductance, and solid plane design. When these fundamentals come together, the product both works stably and passes EMC compliance much more easily. When planning the supply and price of the decoupling capacitors you'll use, you can upload your bill of materials to the BOM tool to price all items at once and see risky parts in advance.